====== Raggedstone1 ====== Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.\\ Here is the product page: http://www.enterpoint.co.uk/moelbryn/raggedstone1.html A colleague and I have the board working using the [[http://www.opencores.org/projects.cgi/web/pci32tlite_oc/overview|pci32tlite_oc]] core from [[http://opencores.org/|opencores.org]] I have written an example linux driver for it that can set hexadecimal numbers to the board's 7segment display. The 7segment display driver (a whishbone bus slave) communicates with the pci core through the (internal) wishbone bus. For more info on the wishbone bus as well as other whishbone compliant cores, go to opencores.org (see above for link). The display driver is written to prevent ghosting on the segments. ===== Linux Kernel Driver ===== Download: * {{rs1linuxdriver-0.0.3.tar.gz|rs1linuxdriver Version 0.0.3}} (released 20070727)\\ * List of [[rs1driver003_changes|changes]] Compilation/Installation/Usage: see README file in archive Older Versions:\\ * {{rs1linuxdriver-0.0.2.tar.gz|rs1linuxdriver Version 0.0.2}} (released 20060302)\\ * List of [[rs1driver002_changes|changes]] * Compilation/Installation/Usage: [[rs1driver|here]]. * {{rs1linuxdriver.tar.gz|rs1linuxdriver Version 0.0.1}} (released 20060118) ===== VHDL/Verilog HDL Code/Bitstreams ===== **Unless indicated otherwise, the files below are for the XC3S400 version of Raggedstone1.** ** Version 0.0.3 ** (released 20070725) Archive contains VHDL Code, ISE Webpack 9.1i (SP3) Project.\\ * Download here: {{rs1_7seg_pci-0.0.3.tar.gz}}\\ * //RS1-1500 (XC3S1500 version)// MCS files: {{xc3s1500proms.zip|}} * (**use only if you have the RS1-1500 board variant!!**) * //Thanks to Marc Bell for providing those// Changes: * Missing PCI lines REQ and GNT are now High-Z (tristated) so they won't keep systems from booting. (also see next point) * similar fixes were also applied to PCI lines STOP, PERR, SERR, and INT due to optimizations by the Xilinx tools those lines were optimized away and thus the inputs/outputs were pulled down (per default, see ''bitgen'' option ''-g UnusedPin:PullDown''). * The same (unused pins pulled down to GND) happened to REQ and GNT as well. The fix now uses the constraint 'SAVE NET FLAG' (see http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0162_123.html for details). I also put some info about how to prevent unused pins from being optimized away [[FPGAUnusedPins|here]] ---- ** Version 0.0.2 ** (released 20060302) Archive contains VHDL Code, ISE Webpack 7.1i Project.\\ Download here: {{rs1_7seg_pci-0.0.2.tar.gz}}\\ //(sorry, I forgot to upload the file. Its now available 20060328)// Version 0.0.2 should load fine on both Windows and Linux, ISE Webpack Versions 7.1i and 8.1i.\\ (I've tested it on Linux/ISE 7.1, Linux/ISE 8.1, and Windows/ISE 8.1)\\ Changes: * converted the VHDL library "onalib" into a regular VHDL file. This should fix errors with onalib. * NO functional changes. (Thats why I didn't include a .bit or .mcs file) //For more info see comments on Version 0.0.1 below.// ---- ** Version 0.0.1 ** Archive contains VHDL Code, ISE Webpack 7.1i Project, bit file, prom file.\\ Download here: {{rs1_7seg_pci-0.0.1.tar.gz}} ---- === Version independent Notes === //**Note:** Most Win* archivers should be able to handle .tar.gz files.\\ If you don't have one, check out the free [[http://www.7-zip.org/|7-zip]]// After unpacking the archive, start Xilinx ISE Webpack, and open the ISE Project file via //File//->//Open Project//.\\ Point it to rs1pcidemo.ise in subdirectory //rs1_7seg+pci-x.y.z/project/rs1pcidemo//. The supplied PROM file //pci_7seg.mcs// can be programmed directly into the XCF02S Prom onboard the Raggedstone1. Oh, BTW, the board is currently using a PCI Vendor ID from Altera. We haven't changed it yet since we downloaded the core from opencores.org Under Linux, the board can be identified by looking at /proc/pci: Bus 1, device 10, function 0: Bridge: PCI device 1172:0100 (Altera Corporation) (rev 130). IRQ 9. Non-prefetchable 32 bit memory at 0xd4000000 [0xd5ffffff]. ---- ==== Tested with ==== === Version 0.0.1 / 0.0.2 === I tested the code in four computers: * an old P75 with a PCI/ISA riser card. It didn't work there, the computer wouldn't even boot. * an PIII 700 with an i810 chipset. It works without problems :-D * another PIII (more info TBD.) * an Intel P4 3GHz, on an Intel D865GBF board * PCI bridge: Intel Corporation 82820 820 (Camino 2) Chipset PCI (rev 194). * Kernel 2.4.4 + RTLinux 3.1 Others tested it on: * Athlon XP 2200+ * PCI bridge: VIA Technologies, Inc. VT8235 PCI Bridge * Linux Kernel 2.6.15 * (Thanks to James of [[http://www.pimpmyrock.com/PimpMyRock/website-creation]] ) === Version 0.0.3 === * Intel Desktop Board D845GEBV2 / Pentium4, 2.4GHz / Intel 82845G chipset * Asus A7V / AMD Duron 750MHz / VIA VT8363 chipset * Gigabyte GA-7DXR+ / AthlonXP 1800+ / AMD-760 chipset (VT82C686A southbridge) * Fujitsu-Siemens Esprimo P5600 / Athlon64 3400+ / SiS 761 (SiS SG86C202 PCI bridge) * Fujitsu-Siemens Scenico L (VKT266)/ AMD AthlonXP 1500+/ VIA VT8366 (Apollo KT266) * EPoX EP-7KXA / AMD Athlon / VIA Apollo KX-133 * Dell Dimension 4100 / Intel PentiumIII / Intel 815 E * Intel Desktop Board D865GBF / Intel Pentium4 3GHz / Intel 865G Chipset (82801 PCI bridge) * has been in (mostly) continuous operation for almost 1.5 years using Version 0.0.1 (but with another Whishbone client, not the 7segment display) * RS1-1500 board variant: mini-ITX PC / Jetway J7F4K running at 1.5GHz ===== FPGA Beginners: Where to go from here ===== Maybe the following tutorial "FPGA design from scratch" is helpful exploring the world of FPGAs: * http://svenand.blogdrive.com/archive/40.html ====== Feedback ====== I'd appreciate feedback...\\ You can contact me via email, my address can be found here: [[WhoAmI]]