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Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
Here is the product page: http://www.enterpoint.co.uk/moelbryn/raggedstone1.html
A colleague and I have the board working using the pci32tlite_oc core from opencores.org
I have written an example linux driver for it that can set hexadecimal numbers to the board's 7segment display.
Download:
Compilation/Installation/Usage: here.
Older Versions:
Version 0.0.1
Archive contains VHDL Code, ISE Webpack 7.1i Project, bit file, prom file.
Download here: rs1_7seg_pci-0.0.1.tar.gz
Note: Most Win* archivers should be able to handle .tar.gz files.
If you don't have one, check out the free 7-zip
After unpacking the archive, start Xilinx ISE Webpack (Version 7.1, 8.1 should also work),
and open the ISE Project file via File→Open Project.
Point it to rs1pcidemo.ise in subdirectory rs1_7seg+pci-0.0.1/project/rs1pcidemo.
The supplied PROM file pci_7seg.mcs can be programmed directly into the XCF02S Prom onboard the Raggedstone1.
I tested the code in two computers:
Oh, BTW, the board is currently using a PCI Vendor ID from Altera. We haven't changed it yet since we downloaded the core from opencores.org
Under Linux, the board can be identified by looking at /proc/pci:
Bus 1, device 10, function 0: Bridge: PCI device 1172:0100 (Altera Corporation) (rev 130). IRQ 9. Non-prefetchable 32 bit memory at 0xd4000000 [0xd5ffffff].
I'd appreciate feedback…
You can contact me via email, my address can be found here: WhoAmI