This shows you the differences between two versions of the page.
raggedstone1 [2007/07/26 19:17] manuel |
raggedstone1 [2014/01/16 20:08] (current) |
||
---|---|---|---|
Line 8: | Line 8: | ||
I have written an example linux driver for it that can set hexadecimal numbers to the board's 7segment display. | I have written an example linux driver for it that can set hexadecimal numbers to the board's 7segment display. | ||
+ | The 7segment display driver (a whishbone bus slave) communicates with the pci core through the (internal) wishbone bus. | ||
+ | For more info on the wishbone bus as well as other whishbone compliant cores, go to opencores.org (see above for link). | ||
+ | The display driver is written to prevent ghosting on the segments. | ||
+ | |||
+ | |||
===== Linux Kernel Driver ===== | ===== Linux Kernel Driver ===== | ||
- | Download: | + | Download: |
- | * {{rs1linuxdriver-0.0.2.tar.gz|rs1linuxdriver Version 0.0.2}} (released 20060302)\\ | + | * {{rs1linuxdriver-0.0.3.tar.gz|rs1linuxdriver Version 0.0.3}} (released 20070727)\\ |
- | * List of [[rs1driver002_changes|changes]] | + | * List of [[rs1driver003_changes|changes]] |
- | Compilation/Installation/Usage: [[rs1driver|here]]. | + | Compilation/Installation/Usage: see README file in archive |
Older Versions:\\ | Older Versions:\\ | ||
+ | * {{rs1linuxdriver-0.0.2.tar.gz|rs1linuxdriver Version 0.0.2}} (released 20060302)\\ | ||
+ | * List of [[rs1driver002_changes|changes]] | ||
+ | * Compilation/Installation/Usage: [[rs1driver|here]]. | ||
* {{rs1linuxdriver.tar.gz|rs1linuxdriver Version 0.0.1}} (released 20060118) | * {{rs1linuxdriver.tar.gz|rs1linuxdriver Version 0.0.1}} (released 20060118) | ||
+ | |||
===== VHDL/Verilog HDL Code/Bitstreams ===== | ===== VHDL/Verilog HDL Code/Bitstreams ===== | ||
+ | |||
+ | **Unless indicated otherwise, the files below are for the XC3S400 version of Raggedstone1.** | ||
** Version 0.0.3 ** (released 20070725) | ** Version 0.0.3 ** (released 20070725) | ||
Archive contains VHDL Code, ISE Webpack 9.1i (SP3) Project.\\ | Archive contains VHDL Code, ISE Webpack 9.1i (SP3) Project.\\ | ||
- | Download here: {{rs1_7seg_pci-0.0.3.tar.gz}}\\ | + | * Download here: {{rs1_7seg_pci-0.0.3.tar.gz}}\\ |
+ | * //RS1-1500 (XC3S1500 version)// MCS files: {{xc3s1500proms.zip|}} | ||
+ | * (**use only if you have the RS1-1500 board variant!!**) | ||
+ | * //Thanks to Marc Bell for providing those// | ||
Changes: | Changes: | ||
Line 81: | Line 95: | ||
---- | ---- | ||
+ | |||
Line 111: | Line 126: | ||
* Intel Desktop Board D865GBF / Intel Pentium4 3GHz / Intel 865G Chipset (82801 PCI bridge) | * Intel Desktop Board D865GBF / Intel Pentium4 3GHz / Intel 865G Chipset (82801 PCI bridge) | ||
* has been in (mostly) continuous operation for almost 1.5 years using Version 0.0.1 (but with another Whishbone client, not the 7segment display) | * has been in (mostly) continuous operation for almost 1.5 years using Version 0.0.1 (but with another Whishbone client, not the 7segment display) | ||
+ | * RS1-1500 board variant: mini-ITX PC / Jetway J7F4K running at 1.5GHz | ||