Xilinx ISE (and probably the other vendor's tools too) removes unused logic and also (more annoyingly) unused pins from FPGA designs.
Unused (or even some static) pins seem to be optimized away by Xilinx' ISE FPGA design tools.
In my specific example, I had a Spartan3 PCI board (see raggedstone1) which, when inserted into a PCI slot, prevented the computer from booting. It turned out that some pins were driven low permanently since they were not used in the PCI core. This core is a target only core, and the signals giving problems were REQ and GNT, which could normally be ignored since they are used by PCI masters only.
There are a few things one can try to prevent this, but not all techniques seem to work well.
Even this method is not great, but it seems to do what we want.
There are two ways to solve the above problem:
Make bitgen set all unused pins to floating:
bitgen -g UnusedPin:Pullnone
or in the ISE GUI:
Generate Programming File” in the ”
Processes” window, select ”
Configuration Options” on the left side.
Unused IOB Pins” to ”
OK” and re-generate your programming file(s).
Make the synthesizer/map&route tools ignore certain signals during optimization, so they can't be optimized away into nothingness.
There are two ways:
Xilinx calls this constraint the ”
SAVE NET FLAG” (see http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0162_123.html)
architecture section, but before the
begin, declare attribute
attribute s: string;
and then one line for each signal (somewhere after the signal has been declared, but before the
attribute s of my_signal_name: signal is "yes";
// synthesis attribute s of my_signal_name is "yes";
In the UCF file, add one line per signal:
NET “my_signal_name” S;
S is short for
SAVE NET FLAG.