VARXEC Projects

Xilinx ISE (and probably the other vendor's tools too) removes unused logic and also (more annoyingly) unused pins from FPGA designs.

Unused (or even some static) pins seem to be optimized away by Xilinx' ISE FPGA design tools.

In my specific example, I had a Spartan3 PCI board (see raggedstone1) which, when inserted into a PCI slot, prevented the computer from booting. It turned out that some pins were driven low permanently since they were not used in the PCI core. This core is a target only core, and the signals giving problems were REQ and GNT, which could normally be ignored since they are used by PCI masters only.

There are a few things one can try to prevent this, but not all techniques seem to work well.
Even this method is not great, but it seems to do what we want.

There are two ways to solve the above problem:

1. have the FPGA tools (Xilinx ISE / bitgen) set unused pins to floating (ie. tristated, not connected)
2. force the pins to be High-Z (tristated) via constraints (either in constraints files, or directly in the source code: VHDL or Verilog)

Make bitgen set all unused pins to floating:

bitgen -g UnusedPin:Pullnone

or in the ISE GUI:

1. Select your toplevel source file
2. Right-click on ”Generate Programming File” in the processes Window, select Properties
3. Then select xxx on the left side.
4. On the right side change yyy to Float
5. Click OK and re-generate programming file(s).

Disadvantages:

• reduces overall Noise Immunity (this is a biggie for many bigger and/or faster designs and thus often not feasible)
• always have to check bitgen options

Make the synthesizer/map&route tools ignore certain signals during optimization, so they can't be optimized away into nothingness. There are two ways:

1. within the source code
2. within the constraints file (.ucf for Xilinx ISE)

Xilinx calls this constraint the SAVE NET FLAG (see http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0162_123.html)

*VHDL* In the architecture section, but before the begin, declare attribute s once:

attribute s: string;

and then one line for each signal (somewhere after the signal has been declared, but before the begin):

attribute s of my_signal_name: signal is "yes"; 

*Verilog*

// synthesis attribute s of my_signal_name is "yes"; 

In the UCF file, add one line per signal:

NET “my_signal_name” S;

S is short for SAVE NET FLAG.