This shows you the differences between two versions of the page.
fpgaunusedpins [2007/07/25 18:45] manuel created |
fpgaunusedpins [2014/01/16 20:08] (current) |
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There are a few things one can try to prevent this, but not all techniques seem to work well.\\ | There are a few things one can try to prevent this, but not all techniques seem to work well.\\ | ||
Even this method is not great, but it seems to do what we want. | Even this method is not great, but it seems to do what we want. | ||
+ | |||
==== Solution ==== | ==== Solution ==== | ||
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bitgen -g UnusedPin:Pullnone | bitgen -g UnusedPin:Pullnone | ||
or in the ISE GUI: | or in the ISE GUI: | ||
- | - Select your toplevel source file | + | - Select your toplevel source file in the ''Sources'' window |
- | - Right-click on "''Generate Programming File''" in the processes Window, select ''Properties'' | + | - Right-click on "''Generate Programming File''" in the "''Processes''" window, select "''Properties...''" |
- | - Then select ''xxx'' on the left side. | + | - Then select "''Configuration Options''" on the left side. |
- | - On the right side change ''yyy'' to ''Float'' | + | - On the right side change "''Unused IOB Pins''" to "''Float''" |
- | - Click OK and re-generate programming file(s). | + | - Click "''OK''" and re-generate your programming file(s). |
Disadvantages: | Disadvantages: | ||
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=== Solution 2 === | === Solution 2 === | ||
- | Make the synthesizer/map&route tools ignore certain signals during optimization, so they can't be optimized away into nothingness. | + | Make the synthesizer/map&route tools ignore certain signals during optimization, so they can't be optimized away into nothingness.\\ |
There are two ways: | There are two ways: | ||
- within the source code | - within the source code | ||
- within the constraints file (.ucf for Xilinx ISE) | - within the constraints file (.ucf for Xilinx ISE) | ||
- | Xilinx calls this constraint the ''SAVE NET FLAG'' (see http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0162_123.html) | + | Xilinx calls this constraint the "''SAVE NET FLAG''" (see http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0162_123.html) |
== Within the Source Code == | == Within the Source Code == | ||
- | *VHDL* | + | __**VHDL**__\\ |
In the ''architecture'' section, but before the ''begin'', declare attribute ''s'' once: | In the ''architecture'' section, but before the ''begin'', declare attribute ''s'' once: | ||
attribute s: string; | attribute s: string; | ||
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attribute s of my_signal_name: signal is "yes"; | attribute s of my_signal_name: signal is "yes"; | ||
- | *Verilog* | + | __**Verilog**__\\ |
// synthesis attribute s of my_signal_name is "yes"; | // synthesis attribute s of my_signal_name is "yes"; | ||