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raggedstone1

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Raggedstone1

Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
Here is the product page: http://www.enterpoint.co.uk/moelbryn/raggedstone1.html

A colleague and I have the board working using the pci32tlite_oc core from opencores.org

I have written an example linux driver for it that can set hexadecimal numbers to the board's 7segment display.

Linux Kernel Driver

Download:

Compilation/Installation/Usage: here.

Older Versions:

VHDL/Verilog HDL Code/Bitstreams

Version 0.0.3 (released 20070725) Archive contains VHDL Code, ISE Webpack 9.1i (SP3) Project.
Download here: rs1_7seg_pci-0.0.3.tar.gz

Changes:

  • Missing PCI lines REQ and GNT are now High-Z (tristated) so they won't keep systems from booting. (also see next point)
  • similar fixes were also applied to PCI lines STOP, PERR, SERR, and INT due to optimizations by the Xilinx tools those lines were optimized away and thus the inputs/outputs were pulled down (per default, see bitgen option -g UnusedPin:PullDown). The same (unused pins pulled down to GND) happened to REQ and GNT as well. The fix now uses the constraint 'SAVE NET FLAG' (see http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0162_123.html for details). I also put some info about unused pins being optimized away here

Version 0.0.2 (released 20060302)

Archive contains VHDL Code, ISE Webpack 7.1i Project.
Download here: rs1_7seg_pci-0.0.2.tar.gz
(sorry, I forgot to upload the file. Its now available 20060328)

Version 0.0.2 should load fine on both Windows and Linux, ISE Webpack Versions 7.1i and 8.1i.
(I've tested it on Linux/ISE 7.1, Linux/ISE 8.1, and Windows/ISE 8.1)

Changes:

  • converted the VHDL library “onalib” into a regular VHDL file. This should fix errors with onalib.
  • NO functional changes. (Thats why I didn't include a .bit or .mcs file)

For more info see comments on Version 0.0.1 below.


Version 0.0.1

Archive contains VHDL Code, ISE Webpack 7.1i Project, bit file, prom file.
Download here: rs1_7seg_pci-0.0.1.tar.gz

Note: Most Win* archivers should be able to handle .tar.gz files.
If you don't have one, check out the free 7-zip

After unpacking the archive, start Xilinx ISE Webpack (Version 7.1, 8.1 should also work), and open the ISE Project file via FileOpen Project.
Point it to rs1pcidemo.ise in subdirectory rs1_7seg+pci-0.0.1/project/rs1pcidemo.

The supplied PROM file pci_7seg.mcs can be programmed directly into the XCF02S Prom onboard the Raggedstone1.


I tested the code in four computers:

  • an old P75 with a PCI/ISA riser card. It didn't work there, the computer wouldn't even boot.
  • an PIII 700 with an i810 chipset. It works without problems :-D
  • another PIII (more info TBD.)
  • an Intel P4 3GHz, on an Intel D865GBF board
    • PCI bridge: Intel Corporation 82820 820 (Camino 2) Chipset PCI (rev 194).
    • Kernel 2.4.4 + RTLinux 3.1

Others tested it on:


Oh, BTW, the board is currently using a PCI Vendor ID from Altera. We haven't changed it yet since we downloaded the core from opencores.org

Under Linux, the board can be identified by looking at /proc/pci:

Bus  1, device  10, function  0:
  Bridge: PCI device 1172:0100 (Altera Corporation) (rev 130).
    IRQ 9.
    Non-prefetchable 32 bit memory at 0xd4000000 [0xd5ffffff].

Feedback

I'd appreciate feedback…
You can contact me via email, my address can be found here: WhoAmI

/var/www/html/data/attic/raggedstone1.1185386971.txt.gz · Last modified: 2014/01/16 20:19 (external edit)