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Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
Here is the product page:

A colleague and I have the board working using the pci32tlite_oc core from

I have written an example linux driver for it that can set hexadecimal numbers to the board's 7segment display.

Linux Kernel Driver


Compilation/Installation/Usage: here.

Older Versions:

VHDL/Verilog HDL Code/Bitstreams

Version 0.0.3 (released 20070725) Archive contains VHDL Code, ISE Webpack 9.1i (SP3) Project.
Download here: rs1_7seg_pci-0.0.3.tar.gz


  • Missing PCI lines REQ and GNT are now High-Z (tristated) so they won't keep systems from booting. (also see next point)
  • similar fixes were also applied to PCI lines STOP, PERR, SERR, and INT due to optimizations by the Xilinx tools those lines were optimized away and thus the inputs/outputs were pulled down (per default, see bitgen option -g UnusedPin:PullDown).

I also put some info about how to prevent unused pins from being optimized away here

Version 0.0.2 (released 20060302)

Archive contains VHDL Code, ISE Webpack 7.1i Project.
Download here: rs1_7seg_pci-0.0.2.tar.gz
(sorry, I forgot to upload the file. Its now available 20060328)

Version 0.0.2 should load fine on both Windows and Linux, ISE Webpack Versions 7.1i and 8.1i.
(I've tested it on Linux/ISE 7.1, Linux/ISE 8.1, and Windows/ISE 8.1)


  • converted the VHDL library “onalib” into a regular VHDL file. This should fix errors with onalib.
  • NO functional changes. (Thats why I didn't include a .bit or .mcs file)

For more info see comments on Version 0.0.1 below.

Version 0.0.1

Archive contains VHDL Code, ISE Webpack 7.1i Project, bit file, prom file.
Download here: rs1_7seg_pci-0.0.1.tar.gz

Version independent Notes

Note: Most Win* archivers should be able to handle .tar.gz files.
If you don't have one, check out the free 7-zip

After unpacking the archive, start Xilinx ISE Webpack, and open the ISE Project file via FileOpen Project.
Point it to rs1pcidemo.ise in subdirectory rs1_7seg+pci-x.y.z/project/rs1pcidemo.

The supplied PROM file pci_7seg.mcs can be programmed directly into the XCF02S Prom onboard the Raggedstone1.

Oh, BTW, the board is currently using a PCI Vendor ID from Altera. We haven't changed it yet since we downloaded the core from

Under Linux, the board can be identified by looking at /proc/pci:

Bus  1, device  10, function  0:
  Bridge: PCI device 1172:0100 (Altera Corporation) (rev 130).
    IRQ 9.
    Non-prefetchable 32 bit memory at 0xd4000000 [0xd5ffffff].

Tested with

Version 0.0.1 / 0.0.2

I tested the code in four computers:

  • an old P75 with a PCI/ISA riser card. It didn't work there, the computer wouldn't even boot.
  • an PIII 700 with an i810 chipset. It works without problems :-D
  • another PIII (more info TBD.)
  • an Intel P4 3GHz, on an Intel D865GBF board
    • PCI bridge: Intel Corporation 82820 820 (Camino 2) Chipset PCI (rev 194).
    • Kernel 2.4.4 + RTLinux 3.1

Others tested it on:

Version 0.0.3

  • Intel Desktop Board D845GEBV2 (82845G chipset, Pentium 4, 2.4GHz)

FPGA Beginners: Where to go from here

Maybe the following tutorial “FPGA design from scratch” is helpful exploring the world of FPGAs:


I'd appreciate feedback…
You can contact me via email, my address can be found here: WhoAmI

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