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Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
Here is the product page: http://www.enterpoint.co.uk/moelbryn/raggedstone1.html
I have written an example linux driver for it that can set hexadecimal numbers to the board's 7segment display. The 7segment display driver (a whishbone bus slave) communicates with the pci core through the (internal) wishbone bus. For more info on the wishbone bus as well as other whishbone compliant cores, go to opencores.org (see above for link). The display driver is written to prevent ghosting on the segments.
Version 0.0.3 (released 20070725)
Archive contains VHDL Code, ISE Webpack 9.1i (SP3) Project.
Download here: rs1_7seg_pci-0.0.3.tar.gz
I also put some info about how to prevent unused pins from being optimized away here
Version 0.0.2 (released 20060302)
Archive contains VHDL Code, ISE Webpack 7.1i Project.
Download here: rs1_7seg_pci-0.0.2.tar.gz
(sorry, I forgot to upload the file. Its now available 20060328)
Version 0.0.2 should load fine on both Windows and Linux, ISE Webpack Versions 7.1i and 8.1i.
(I've tested it on Linux/ISE 7.1, Linux/ISE 8.1, and Windows/ISE 8.1)
For more info see comments on Version 0.0.1 below.
Archive contains VHDL Code, ISE Webpack 7.1i Project, bit file, prom file.
Download here: rs1_7seg_pci-0.0.1.tar.gz
Note: Most Win* archivers should be able to handle .tar.gz files.
If you don't have one, check out the free 7-zip
After unpacking the archive, start Xilinx ISE Webpack,
and open the ISE Project file via File→Open Project.
Point it to rs1pcidemo.ise in subdirectory rs1_7seg+pci-x.y.z/project/rs1pcidemo.
The supplied PROM file pci_7seg.mcs can be programmed directly into the XCF02S Prom onboard the Raggedstone1.
Oh, BTW, the board is currently using a PCI Vendor ID from Altera. We haven't changed it yet since we downloaded the core from opencores.org
Under Linux, the board can be identified by looking at /proc/pci:
Bus 1, device 10, function 0: Bridge: PCI device 1172:0100 (Altera Corporation) (rev 130). IRQ 9. Non-prefetchable 32 bit memory at 0xd4000000 [0xd5ffffff].
I tested the code in four computers:
Others tested it on:
Maybe the following tutorial “FPGA design from scratch” is helpful exploring the world of FPGAs:
I'd appreciate feedback…
You can contact me via email, my address can be found here: WhoAmI